drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

314

#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

315

#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h

1013

#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h

1103

#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h

1123

#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h

1629

#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00

drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_sh_mask.h

295

#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h

600

#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h

599

#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h

608

#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h

602

#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L