drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

310

#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

311

#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h

1012

#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h

1102

#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h

1122

#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h

1628

#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_sh_mask.h

291

#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h

596

#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h

595

#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h

604

#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h

598

#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0