drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

313

#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

314

#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h

1011

#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf

drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h

1101

#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h

1121

#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf

drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h

1627

#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0xf

drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_0_sh_mask.h

294

#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h

599

#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h

598

#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h

607

#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL

drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h

601

#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL