drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

33524

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

32572

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

34367

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

37610

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

29995

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

20101

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

19299

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

23075

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

24362

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

24415

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

26672

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

7240

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

7851

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

8759

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

9311

#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000