drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

33516

#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

32564

#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

34358

#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

37601

#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

29986

#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

20092

#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

19290

#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

23067

#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

24354

#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

24407

#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

21857

#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

26664

#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

7230

#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

7841

#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

8743

#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

9295

#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2