drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

23068

#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

24355

#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

24408

#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

21858

#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

26665

#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

7226

#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

7843

#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

8745

#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

9297

#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4