Symbol: RLC_MGCG_CTRL__SPARE_MASK
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h
33392
#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h
32366
#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h
34189
#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFF8000L
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h
37432
#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFF8000L
drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h
29817
#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFF8000L
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h
19921
#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFF8000L
drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h
19078
#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFF8000L
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
22938
#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h
24225
#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h
24236
#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h
21696
#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h
26497
#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFE0000L
drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h
9061
#define RLC_MGCG_CTRL__SPARE_MASK 0xffff8000
drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h
9605
#define RLC_MGCG_CTRL__SPARE_MASK 0xfffe0000