drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

33247

#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

32195

#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

35842

#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

39172

#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

31400

#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

21425

#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

20704

#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

22777

#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

24064

#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

24067

#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

21541

#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

26328

#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

7198

#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

7731

#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

8545

#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

9097

#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2