drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

33577

#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

32609

#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

34435

#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

37728

#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

30063

#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

20167

#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

19365

#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

23120

#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

24407

#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

24468

#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

21917

#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

26729

#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

7067

#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x00000001

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

7890

#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

8808

#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

9358

#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1