drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

33589

#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

32621

#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

34447

#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

37740

#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

30075

#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

20179

#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

19377

#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

23132

#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

24419

#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

24480

#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

21929

#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

26741

#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

7064

#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

7897

#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

8815

#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

9365

#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000