drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

33576

#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

32608

#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

34434

#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

37727

#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

30062

#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

20166

#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

19364

#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

23119

#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

24406

#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

24467

#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

21916

#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

26728

#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

7061

#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x00000000

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

7888

#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

8806

#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

9356

#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0