drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

33584

#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

32616

#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

34442

#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

37735

#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

30070

#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

20174

#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

19372

#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

23127

#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

24414

#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

24475

#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

21924

#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

26736

#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

7060

#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

7887

#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

8805

#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

9355

#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1