drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

33665

#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

32697

#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

34499

#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

37792

#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

30127

#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

20228

#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

19431

#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

23208

#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

24495

#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

24556

#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

22005

#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

26817

#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

7052

#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

7963

#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

8881

#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

9431

#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000