drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

33663

#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

32695

#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

34497

#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

37790

#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

30125

#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

20226

#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

19429

#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

23206

#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

24493

#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

24554

#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

22003

#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

26815

#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

7048

#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

7959

#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

8877

#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

9427

#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4