drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

33661

#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

32693

#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

34495

#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

37788

#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

30123

#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

20224

#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

19427

#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

23204

#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

24491

#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

24552

#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

22001

#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

26813

#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

7046

#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

7955

#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

8873

#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

9423

#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1