arch/mips/n64/init.c

53

#define REG_BASE ((u32 *) CKSEG1ADDR(0x4400000))

arch/mips/n64/init.c

60

#undef REG_BASE

drivers/atm/iphase.h

632

#define REG_BASE IPHASE5575_BUS_CONTROL_REG_BASE

drivers/atm/midway.h

23

#define REG_BASE 0x00040000 /* offset of Midway register area */

drivers/pinctrl/qcom/pinctrl-msm8976.c

14

#define REG_BASE 0x0

drivers/pinctrl/qcom/pinctrl-msm8996.c

12

#define REG_BASE 0x0

drivers/pinctrl/qcom/pinctrl-qdu1000.c

13

#define REG_BASE 0x100000

drivers/pinctrl/qcom/pinctrl-sa8775p.c

13

#define REG_BASE 0x100000

drivers/pinctrl/qcom/pinctrl-sdx65.c

12

#define REG_BASE 0x0

drivers/pinctrl/qcom/pinctrl-sdx75.c

11

#define REG_BASE 0x100000

drivers/pinctrl/qcom/pinctrl-sm6375.c

13

#define REG_BASE 0x100000