arch/arm/probes/decode.h

263

#define REGS(r16, r12, r8, r4, r0) \

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

37

#define REGS dmub->regs

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c

36

#define REGS dmub->regs

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c

37

#define REGS dmub->regs

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c

36

#define REGS dmub->regs

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn302.c

36

#define REGS dmub->regs

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.c

37

#define REGS dmub->regs

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

36

#define REGS dmub->regs_dcn31

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c

42

#define REGS dmub->regs_dcn31

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn315.c

42

#define REGS dmub->regs_dcn31

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn316.c

42

#define REGS dmub->regs_dcn31

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

37

#define REGS dmub->regs_dcn32

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

37

#define REGS dmub->regs_dcn35

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.c

13

#define REGS dmub->regs_dcn35

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.c

13

#define REGS dmub->regs_dcn35

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

16

#define REGS dmub->regs_dcn401

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h

299

#define REGS(_array, _sel_reg, _sel_val) \

drivers/media/i2c/ar0521.c

672

#define REGS(...) REGS_ENTRY(((const __be16[]){__VA_ARGS__}))

drivers/media/i2c/imx258.c

532

#define REGS(_list) { .num_of_regs = ARRAY_SIZE(_list), .regs = _list, }

drivers/memory/tegra/tegra210-emc-cc-r21021.c

33

#define REGS (1 << 30)

sound/pci/ali5451/ali5451.c

159

struct REGS {