drivers/clk/clk-stm32f4.c

514

PLL,

drivers/clk/mediatek/clk-mt2701.c

921

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \

drivers/clk/mediatek/clk-mt2712-apmixedsys.c

44

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \

drivers/clk/mediatek/clk-mt6735-apmixedsys.c

47

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _rst_bar_mask, \

drivers/clk/mediatek/clk-mt6765.c

695

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \

drivers/clk/mediatek/clk-mt6779.c

1172

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \

drivers/clk/mediatek/clk-mt6795-apmixedsys.c

26

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \

drivers/clk/mediatek/clk-mt6797.c

619

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \

drivers/clk/mediatek/clk-mt7622-apmixedsys.c

41

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \

drivers/clk/mediatek/clk-mt7629.c

44

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \

drivers/clk/mediatek/clk-mt7981-apmixed.c

38

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \

drivers/clk/mediatek/clk-mt7986-apmixed.c

36

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \

drivers/clk/mediatek/clk-mt7988-apmixed.c

22

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, _pd_reg, \

drivers/clk/mediatek/clk-mt8135-apmixedsys.c

20

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \

drivers/clk/mediatek/clk-mt8167-apmixedsys.c

42

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \

drivers/clk/mediatek/clk-mt8173-apmixedsys.c

44

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \

drivers/clk/mediatek/clk-mt8183-apmixedsys.c

81

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \

drivers/clk/mediatek/clk-mt8186-apmixedsys.c

19

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \

drivers/clk/mediatek/clk-mt8188-apmixedsys.c

32

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \

drivers/clk/mediatek/clk-mt8192-apmixedsys.c

35

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \

drivers/clk/mediatek/clk-mt8195-apmixedsys.c

33

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \

drivers/clk/mediatek/clk-mt8195-apusys_pll.c

28

#define PLL(_id, _name, _reg, _pwr_reg, _pd_reg, _pcw_reg) { \

drivers/clk/mediatek/clk-mt8196-mcu.c

45

#define PLL(_id, _name, _reg, _en_reg, _en_mask, _pll_en_bit, \

drivers/clk/mediatek/clk-mt8196-mfg.c

37

#define PLL(_id, _name, _reg, _en_reg, _en_mask, _pll_en_bit, \

drivers/clk/mediatek/clk-mt8365-apmixedsys.c

45

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \

drivers/clk/mediatek/clk-mt8516-apmixedsys.c

43

#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \

drivers/clk/pistachio/clk.h

119

#define PLL(_id, _name, _pname, _type, _reg, _rates) \

drivers/clk/rockchip/clk.h

635

#define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \

drivers/clk/samsung/clk.h

296

#define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable) \

drivers/clk/stm32/clk-stm32mp1.c

1237

#define PLL(_id, _name, _parents, _flags, _offset_p, _offset_mux)\

drivers/net/wireless/broadcom/brcm80211/brcmsmac/aiutils.h

104

#define PLL 0x2 /* main chip pll */