drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

7536

#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

7859

#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

24113

#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

26459

#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

20154

#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

31873

#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

32495

#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

1968

#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

1826

#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

1823

#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

15350

#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

1927

#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c