PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK
#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000e0L
#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0
#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0
#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0xe0
#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000E0L
#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000E0L
#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000E0L
#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000E0L
#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000E0L
#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000E0L
#define PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK 0x000000E0L