drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h

7128

#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h

3265

#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000

drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h

11013

#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000

drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h

4219

#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x1000

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h

53828

#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h

31577

#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h

38045

#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h

42685

#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/pcie/pcie_6_1_0_sh_mask.h

712

#define PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK 0x00001000L