drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h

7108

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x00000004

drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h

3254

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h

11002

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h

4208

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h

53796

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h

31547

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h

38013

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h

42653

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4

drivers/gpu/drm/amd/include/asic_reg/pcie/pcie_6_1_0_sh_mask.h

680

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

74

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

81

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

95

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4