drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h

7107

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L

drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h

3253

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70

drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h

11001

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70

drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h

4207

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x70

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h

53822

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h

31571

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h

38039

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h

42679

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L

drivers/gpu/drm/amd/include/asic_reg/pcie/pcie_6_1_0_sh_mask.h

706

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L

drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

73

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

80

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

94

#define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L