drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h

7105

#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x00000011

drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h

3276

#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h

11024

#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h

4230

#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h

53807

#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h

31557

#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h

38024

#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h

42664

#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11

drivers/gpu/drm/amd/include/asic_reg/pcie/pcie_6_1_0_sh_mask.h

691

#define PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN__SHIFT 0x11