drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h

7099

#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x00000015

drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h

3284

#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h

11032

#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h

4238

#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h

53811

#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h

31561

#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h

38028

#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h

42668

#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15

drivers/gpu/drm/amd/include/asic_reg/pcie/pcie_6_1_0_sh_mask.h

695

#define PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT 0x15