drivers/gpu/drm/amd/include/asic_reg/bif/bif_3_0_sh_mask.h

7051

#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x00000008

drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h

3010

#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h

10742

#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h

3964

#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h

53707

#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h

31459

#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h

37924

#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h

42564

#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8

drivers/gpu/drm/amd/include/asic_reg/pcie/pcie_6_1_0_sh_mask.h

592

#define PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT 0x8