drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

7501

#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

7824

#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

24388

#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

26742

#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

20437

#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

32148

#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

32721

#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

1863

#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

1721

#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

1718

#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

15245

#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

1822

#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL