drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

7483

#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

7806

#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

24346

#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

26698

#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

20395

#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

32104

#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

32677

#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

1845

#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

1703

#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

1700

#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

15227

#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

1804

#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

6403

#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x00000006

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

6612

#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

7400

#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

7954

#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6