drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

38

#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_3_1_sh_mask.h

20280

#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h

19480

#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h

57130

#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_11_0_sh_mask.h

53154

#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_2_0_sh_mask.h

48330

#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h

25154

#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_7_0_sh_mask.h

44953

#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_9_0_sh_mask.h

18787

#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK 0x00001000L