drivers/gpu/drm/amd/include/asic_reg/bif/bif_4_1_sh_mask.h

560

#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_0_sh_mask.h

588

#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/bif/bif_5_1_sh_mask.h

558

#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h

2382

#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_2_3_sh_mask.h

1721

#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h

17489

#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_sh_mask.h

17624

#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_sh_mask.h

117900

#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0

drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h

20479

#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0