drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1439

#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1442

#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2356

#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

1964

#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6258

#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

7061

#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6084

#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5297

#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

7319

#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18