drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_7_0_sh_mask.h

501

#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h

1023

#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_0_0_sh_mask.h

1364

#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_sh_mask.h

1367

#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_6_0_sh_mask.h

2281

#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_3_0_0_sh_mask.h

1889

#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_0_sh_mask.h

6178

#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_3_sh_mask.h

6909

#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_4_0_5_sh_mask.h

6004

#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_0_0_sh_mask.h

5236

#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL

drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_5_3_0_sh_mask.h

7258

#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL