drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

200

#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

207

#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

196

#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

195

#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

197

#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

202

#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

206

#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

194

#define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

173

#define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

172

#define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

186

#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\