drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

49

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

45

#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

55

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

46

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

49

#define BASE_INNER(seg) MP1_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

91

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

99

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

130

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

46

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

49

#define BASE_INNER(seg) MP1_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

49

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

28

#define BASE_INNER(seg) \

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

53

#define BASE_INNER(seg) \

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

44

#define BASE_INNER(seg) \

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

50

#define BASE_INNER(seg) \

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

44

#define BASE_INNER(seg) \

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

52

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

53

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

49

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

50

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

50

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

51

#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

49

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

50

#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

59

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

60

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

54

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

55

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

56

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

57

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

49

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

50

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

52

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

53

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

47

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

48

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

32

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

33

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

22

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

23

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

65

#define BASE_INNER(seg) \

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

162

#define BASE_INNER(seg) \

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

163

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

164

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

112

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

113

#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

170

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

171

#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

177

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

178

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

164

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

165

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

110

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

111

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

166

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

167

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

168

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

169

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

173

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

174

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

177

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

178

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

165

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

166

#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

144

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

145

#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

143

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

144

#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

157

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

158

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

124

#define BASE_INNER(seg) \

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

107

#define BASE_INNER(seg) \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

125

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

247

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

248

#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

98

#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

114

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

113

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

176

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

172

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

125

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

141

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

142

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

159

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

145

#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

114

#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

114

#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

127

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

128

#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

107

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

108

#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

112

#undef BASE_INNER

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

113

#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

95

#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

35

#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c

34

#define BASE_INNER(seg) DMU_BASE__INST0_SEG##seg

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c

35

#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn301.c

34

#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn302.c

34

#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn303.c

35

#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

34

#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c

40

#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn315.c

40

#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn316.c

40

#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

35

#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

35

#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.c

11

#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.c

11

#define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

14

#define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg