arch/mips/kernel/traps.c

505

#define BASE 0x03e00000

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

51

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c

47

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

57

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c

51

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

93

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn351_clk_mgr.c

101

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

132

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_smu.c

51

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

51

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

31

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c

57

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c

48

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c

54

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c

48

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c

55

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c

52

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c

53

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c

52

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_factory_dcn30.c

62

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c

57

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c

59

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c

52

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_factory_dcn32.c

55

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/gpio/dcn32/hw_translate_dcn32.c

50

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_factory_dcn401.c

35

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/gpio/dcn401/hw_translate_dcn401.c

25

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c

68

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c

165

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c

167

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

115

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c

118

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

174

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/irq/dcn30/irq_service_dcn30.c

181

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/irq/dcn302/irq_service_dcn302.c

168

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/irq/dcn303/irq_service_dcn303.c

114

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/irq/dcn31/irq_service_dcn31.c

170

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/irq/dcn314/irq_service_dcn314.c

172

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c

177

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/irq/dcn32/irq_service_dcn32.c

181

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/irq/dcn35/irq_service_dcn35.c

169

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/irq/dcn351/irq_service_dcn351.c

148

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/irq/dcn36/irq_service_dcn36.c

147

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/irq/dcn401/irq_service_dcn401.c

161

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

134

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

110

#define BASE(seg) \

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

127

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

250

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

100

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

116

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

115

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

178

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

174

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

127

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

144

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

161

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

147

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

116

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

116

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

130

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

110

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

115

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

97

#define BASE(seg) BASE_INNER(seg)

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

35

#define BASE(seg) BASE_INNER(seg)

drivers/hwmon/pc87360.c

75

#define BASE 0x60 /* Register: Base address */

drivers/media/pci/cobalt/cobalt-omnitek.c

42

#define BASE (cobalt->bar0)

drivers/media/tuners/xc2028-types.h

14

#define BASE (1<<0)

drivers/net/ethernet/smsc/smc9194.h

99

#define BASE 2

drivers/ps3/ps3av_cmd.c

489

#define BASE PS3AV_CMD_AUDIO_FS_44K

drivers/ps3/ps3av_cmd.c

547

#undef BASE

include/linux/zutil.h

53

#define BASE 65521L /* largest prime smaller than 65536 */

tools/testing/selftests/bpf/test_sockmap.c

1044

BASE,