drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

10558

#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

10312

#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

38447

#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xFFFFFFF0L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

36822

#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xFFFFFFF0L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

33702

#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xFFFFFFF0L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

38380

#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x000000F0L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

40600

#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x000000F0L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

6091

#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

5563

#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

5398

#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

21487

#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_3_sh_mask.h

6601

#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h

4236

#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h

4181

#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h

4909

#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000

drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h

5439

#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000