drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20783

#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18889

#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

25402

#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

27917

#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

21465

#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

7848

#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

10167

#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

13299

#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14602

#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14456

#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

6724

#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L