drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20781

#define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18880

#define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT 0xe

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

25392

#define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

27907

#define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

21455

#define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

7838

#define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

10157

#define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT 0xf

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

6721

#define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT 0x1e