drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20782

#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18888

#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

25401

#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

27916

#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

21464

#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

7847

#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

10166

#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

13298

#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14601

#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14455

#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

6723

#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L