drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h

20787

#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h

18893

#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_sh_mask.h

25406

#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_3_sh_mask.h

27921

#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_5_0_sh_mask.h

21468

#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_0_0_sh_mask.h

7852

#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h

10171

#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000400L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h

13303

#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h

14606

#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h

14460

#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L

drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_2_sh_mask.h

6728

#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000200L