usr/src/uts/common/io/iwp/iwp.c

4965

iwp_reg_write(sc, (IWP_SCD_BASE + 0x10),

usr/src/uts/common/io/iwp/iwp_hw.h

2584

#define IWP_SCD_SRAM_BASE_ADDR (IWP_SCD_BASE + 0x0)

usr/src/uts/common/io/iwp/iwp_hw.h

2585

#define IWP_SCD_DRAM_BASE_ADDR (IWP_SCD_BASE + 0x8)

usr/src/uts/common/io/iwp/iwp_hw.h

2586

#define IWP_SCD_QUEUECHAIN_SEL (IWP_SCD_BASE + 0xE8)

usr/src/uts/common/io/iwp/iwp_hw.h

2587

#define IWP_SCD_AGGR_SEL (IWP_SCD_BASE + 0x248)

usr/src/uts/common/io/iwp/iwp_hw.h

2588

#define IWP_SCD_QUEUE_RDPTR(x) (IWP_SCD_BASE + 0x68 + (x) * 4)

usr/src/uts/common/io/iwp/iwp_hw.h

2589

#define IWP_SCD_INTERRUPT_MASK (IWP_SCD_BASE + 0x108)

usr/src/uts/common/io/iwp/iwp_hw.h

2590

#define IWP_SCD_TXFACT (IWP_SCD_BASE + 0x1C)

usr/src/uts/common/io/iwp/iwp_hw.h

2591

#define IWP_SCD_QUEUE_STATUS_BITS(x) (IWP_SCD_BASE + 0x10C + (x) * 4)