IWP_CMD_QUEUE_NUM
if (IWP_CMD_QUEUE_NUM == i) {
err = iwp_alloc_tx_ring(sc, &sc->sc_txq[IWP_CMD_QUEUE_NUM],
TFD_CMD_SLOTS, IWP_CMD_QUEUE_NUM);
iwp_tx_ring_t *ring = &sc->sc_txq[IWP_CMD_QUEUE_NUM];
iwp_tx_ring_t *ring = &sc->sc_txq[IWP_CMD_QUEUE_NUM];
IWP_WRITE(sc, HBUS_TARG_WRPTR, (IWP_CMD_QUEUE_NUM << 8));
iwp_reg_write(sc, IWP_SCD_QUEUE_RDPTR(IWP_CMD_QUEUE_NUM), 0);
iwp_reg_write(sc, IWP_SCD_QUEUE_STATUS_BITS(IWP_CMD_QUEUE_NUM),
(~(1 << IWP_CMD_QUEUE_NUM)))