IWK_WRITE
IWK_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
IWK_WRITE(sc, IWK_FH_TCSR_CHNL_TX_CONFIG_REG(ring->qid), 0);
IWK_WRITE(sc, CSR_GP_CNTRL,
IWK_WRITE(sc, CSR_GP_CNTRL,
IWK_WRITE(sc, HBUS_TARG_MEM_RADDR, addr);
IWK_WRITE(sc, HBUS_TARG_MEM_WADDR, addr);
IWK_WRITE(sc, HBUS_TARG_MEM_WDAT, data);
IWK_WRITE(sc, HBUS_TARG_PRPH_RADDR, addr | (3 << 24));
IWK_WRITE(sc, HBUS_TARG_PRPH_WADDR, addr | (3 << 24));
IWK_WRITE(sc, HBUS_TARG_PRPH_WDAT, data);
IWK_WRITE(sc, HBUS_TARG_WRPTR, (i << 8));
IWK_WRITE(sc, CSR_INT_MASK, 0);
IWK_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, index & (~7));
IWK_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
IWK_WRITE(sc, CSR_INT_MASK, 0);
IWK_WRITE(sc, CSR_INT, r);
IWK_WRITE(sc, CSR_FH_INT_STATUS, rfh);
IWK_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
IWK_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
IWK_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
IWK_WRITE(sc, HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
IWK_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_STOP_MASTER);
IWK_WRITE(sc, CSR_INT, 0xffffffff);
IWK_WRITE(sc, CSR_GIO_CHICKEN_BITS,
IWK_WRITE(sc, CSR_GP_CNTRL, tmp | CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
IWK_WRITE(sc, CSR_INT_COALESCING, 512 / 32); /* ??? */
IWK_WRITE(sc, CSR_SW_VER, tmp);
IWK_WRITE(sc, CSR_HW_IF_CONFIG_REG,
IWK_WRITE(sc, CSR_HW_IF_CONFIG_REG,
IWK_WRITE(sc, CSR_EEPROM_REG, addr<<1);
IWK_WRITE(sc, CSR_EEPROM_REG, tmp & ~(0x2));
IWK_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
IWK_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
IWK_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
IWK_WRITE(sc, FH_RSCSR_CHNL0_STTS_WPTR_REG,
IWK_WRITE(sc, FH_MEM_RCSR_CHNL0_CONFIG_REG,
IWK_WRITE(sc, FH_RSCSR_CHNL0_RBDCB_WPTR_REG,
IWK_WRITE(sc, FH_MEM_CBBC_QUEUE(qid),
IWK_WRITE(sc, IWK_FH_TCSR_CHNL_TX_CONFIG_REG(qid),
IWK_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
IWK_WRITE(sc, CSR_UCODE_DRV_GP1_CLR,
IWK_WRITE(sc, CSR_INT, 0xffffffff);
IWK_WRITE(sc, CSR_INT_MASK, CSR_INI_SET_MASK);
IWK_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
IWK_WRITE(sc, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
IWK_WRITE(sc, CSR_RESET, 0);
IWK_WRITE(sc, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
IWK_WRITE(sc, CSR_INT_MASK, 0);
IWK_WRITE(sc, CSR_INT, CSR_INI_SET_MASK);
IWK_WRITE(sc, CSR_FH_INT_STATUS, 0xffffffff);
IWK_WRITE(sc, CSR_RESET, tmp | CSR_RESET_REG_FLAG_SW_RESET);