usr/src/uts/common/io/iwh/iwh.c

5349

iwh_reg_write(sc, (IWH_SCD_BASE + 0x10),

usr/src/uts/common/io/iwh/iwh_hw.h

2586

#define IWH_SCD_SRAM_BASE_ADDR (IWH_SCD_BASE + 0x0)

usr/src/uts/common/io/iwh/iwh_hw.h

2587

#define IWH_SCD_DRAM_BASE_ADDR (IWH_SCD_BASE + 0x8)

usr/src/uts/common/io/iwh/iwh_hw.h

2588

#define IWH_SCD_QUEUECHAIN_SEL (IWH_SCD_BASE + 0xE8)

usr/src/uts/common/io/iwh/iwh_hw.h

2589

#define IWH_SCD_AGGR_SEL (IWH_SCD_BASE + 0x248)

usr/src/uts/common/io/iwh/iwh_hw.h

2590

#define IWH_SCD_QUEUE_RDPTR(x) (IWH_SCD_BASE + 0x68 + (x) * 4)

usr/src/uts/common/io/iwh/iwh_hw.h

2591

#define IWH_SCD_INTERRUPT_MASK (IWH_SCD_BASE + 0x108)

usr/src/uts/common/io/iwh/iwh_hw.h

2592

#define IWH_SCD_TXFACT (IWH_SCD_BASE + 0x1C)

usr/src/uts/common/io/iwh/iwh_hw.h

2593

#define IWH_SCD_QUEUE_STATUS_BITS(x) (IWH_SCD_BASE + 0x10C + (x) * 4)