IWH_CMD_QUEUE_NUM
if (IWH_CMD_QUEUE_NUM == i) {
err = iwh_alloc_tx_ring(sc, &sc->sc_txq[IWH_CMD_QUEUE_NUM],
TFD_CMD_SLOTS, IWH_CMD_QUEUE_NUM);
iwh_tx_ring_t *ring = &sc->sc_txq[IWH_CMD_QUEUE_NUM];
iwh_tx_ring_t *ring = &sc->sc_txq[IWH_CMD_QUEUE_NUM];
IWH_WRITE(sc, HBUS_TARG_WRPTR, (IWH_CMD_QUEUE_NUM << 8));
iwh_reg_write(sc, IWH_SCD_QUEUE_RDPTR(IWH_CMD_QUEUE_NUM), 0);
iwh_reg_write(sc, IWH_SCD_QUEUE_STATUS_BITS(IWH_CMD_QUEUE_NUM),
(~(1 << IWH_CMD_QUEUE_NUM)))