INT64_C
#define INTMAX_C(c) INT64_C(c)
for (; (INT64_C(1) << mul) <= nsize; j++, mul += 10)
if (!(nsize & ((INT64_C(1) << (mul - 10)) - 1))) {
if (dp->d_mof < INT64_C(0))
eid->eid_ts = INT64_C(0);
eid->eid_ts = INT64_C(0);
#define VA13 INT64_C(0x0000000000000002)
#define DCU_IPS_MASK INT64_C(0x0030000000000000)
#define CH_ICPATAG_MASK INT64_C(0x000007ffffffe000)
#define CH_ICUTAG_MASK INT64_C(0x00000000001fe000)
#define CH_ICSNTAG_MASK INT64_C(0x000007ffffffe000)
#define CH_ICLOWER_VALID INT64_C(0x0004000000000000)
#define CH_ICUPPER_VALID INT64_C(0x0004000000000000)
#define CHP_ICPATAG_MASK INT64_C(0x000003ffffffe000)
#define CHP_ICSNTAG_MASK INT64_C(0x000003ffffffe000)
#define CHP_ICUTAG_MASK INT64_C(0x00000000001fe000)
#define PN_ICUTAG_MASK INT64_C(0x00000000003fc000)
#define CHP_ICWAY_MASK INT64_C(0x0000000000003fe0)
#define CHP_ICPATAG_PARMASK INT64_C(0x0000003fffffff00)
#define CHP_ICSNTAG_PARMASK INT64_C(0x0000003fffffff00)
#define CH_ICDATA_PRED_ISPCREL INT64_C(0x0000008000000000)
#define CHP_ICDATA_PCREL_PARMASK INT64_C(0x0000039ffffff800)
#define CHP_ICDATA_NPCREL_PARMASK INT64_C(0x000003bfffffffff)
#define PN_ICDATA_PARITY_BIT_MASK INT64_C(0x40000000000)
#define SAFARI_CONFIG_ECLK_1 INT64_C(0x0000000000000000) /* 1/1 clock */
#define SAFARI_CONFIG_ECLK_2 INT64_C(0x0000000040000000) /* 1/2 clock */
#define SAFARI_CONFIG_ECLK_32 INT64_C(0x0000000080000000) /* 1/32 clock */
#define MCU_ACT_STATUS INT64_C(0x0000000000000001)
#define JBUS_CONFIG_ECLK_1 INT64_C(0x0000000000000000) /* 1/1 clock */
#define SIU_ACT_STATUS INT64_C(0x0000000000000002)
#define JBUS_CONFIG_ECLK_2 INT64_C(0x0000000000002000) /* 1/2 clock */
#define JBUS_CONFIG_ECLK_32 INT64_C(0x0000000000004000) /* 1/32 clock */
#define JP_MCU_FSM_MASK INT64_C(0x0000000006000000) /* 26..25 */
#define C_AFSR_TUE_SH INT64_C(0x4000000000000000) /* uncorrectable tag UE */
#define C_AFSR_IMC INT64_C(0x2000000000000000) /* intr vector MTAG ECC */
#define C_AFSR_IMU INT64_C(0x1000000000000000) /* intr vector MTAG ECC */
#define C_AFSR_DTO INT64_C(0x0800000000000000) /* disrupting TO error */
#define C_AFSR_DBERR INT64_C(0x0400000000000000) /* disrupting BERR error */
#define C_AFSR_THCE INT64_C(0x0200000000000000) /* h/w correctable E$ tag err */
#define C_AFSR_TSCE INT64_C(0x0100000000000000) /* s/w correctable E$ tag err */
#define C_AFSR_TUE INT64_C(0x0080000000000000) /* uncorrectable E$ tag error */
#define C_AFSR_DUE INT64_C(0x0040000000000000) /* disrupting UE error */
#define C_AFSR_ME INT64_C(0x0020000000000000) /* errors > 1, same type!=CE */
#define C_AFSR_PRIV INT64_C(0x0010000000000000) /* priv code access error */
#define C_AFSR_PERR INT64_C(0x0008000000000000) /* system interface protocol */
#define C_AFSR_IERR INT64_C(0x0004000000000000) /* internal system interface */
#define C_AFSR_ISAP INT64_C(0x0002000000000000) /* system request parity err */
#define C_AFSR_EMC INT64_C(0x0001000000000000) /* mtag with CE error */
#define C_AFSR_EMU INT64_C(0x0000800000000000) /* mtag with UE error */
#define C_AFSR_IVC INT64_C(0x0000400000000000) /* intr vector with CE error */
#define C_AFSR_IVU INT64_C(0x0000200000000000) /* intr vector with UE error */
#define C_AFSR_TO INT64_C(0x0000100000000000) /* bus timeout from sys bus */
#define C_AFSR_BERR INT64_C(0x0000080000000000) /* bus error from system bus */
#define C_AFSR_UCC INT64_C(0x0000040000000000) /* E$ with software CE error */
#define C_AFSR_UCU INT64_C(0x0000020000000000) /* E$ with software UE error */
#define C_AFSR_CPC INT64_C(0x0000010000000000) /* copyout with CE error */
#define C_AFSR_CPU INT64_C(0x0000008000000000) /* copyout with UE error */
#define C_AFSR_WDC INT64_C(0x0000004000000000) /* writeback ecache CE error */
#define C_AFSR_WDU INT64_C(0x0000002000000000) /* writeback ecache UE error */
#define C_AFSR_EDC INT64_C(0x0000001000000000) /* ecache CE ECC error */
#define C_AFSR_EDU INT64_C(0x0000000800000000) /* ecache UE ECC error */
#define C_AFSR_UE INT64_C(0x0000000400000000) /* uncorrectable ECC error */
#define C_AFSR_CE INT64_C(0x0000000200000000) /* correctable ECC error */
#define C_AFSR_M_SYND INT64_C(0x00000000000f0000) /* mtag ECC syndrome */
#define C_AFSR_E_SYND INT64_C(0x00000000000001ff) /* data ECC syndrome */
#define C_AFSR_RED_ERR INT64_C(0x0000000000002000) /* redunancy Efuse error */
#define C_AFSR_EFA_PAR_ERR INT64_C(0x0000000000001000) /* Efuse parity error */
#define C_AFSR_L3_MECC INT64_C(0x0000000000000800) /* L3 address parity */
#define C_AFSR_L3_THCE INT64_C(0x0000000000000400) /* tag CE */
#define C_AFSR_L3_TUE_SH INT64_C(0x0000000000000200) /* tag UE from snp/cpy */
#define C_AFSR_L3_TUE INT64_C(0x0000000000000100) /* tag UE */
#define C_AFSR_L3_EDC INT64_C(0x0000000000000080) /* L3 cache CE */
#define C_AFSR_L3_EDU INT64_C(0x0000000000000040) /* L3 cache UE */
#define C_AFSR_L3_UCC INT64_C(0x0000000000000020) /* software recover CE */
#define C_AFSR_L3_UCU INT64_C(0x0000000000000010) /* software recover UE */
#define C_AFSR_L3_CPC INT64_C(0x0000000000000008) /* copyout with CE */
#define C_AFSR_L3_CPU INT64_C(0x0000000000000004) /* copyout with UE */
#define C_AFSR_L3_WDC INT64_C(0x0000000000000002) /* writeback CE */
#define C_AFSR_L3_WDU INT64_C(0x0000000000000001) /* writeback UE */
#define C_AFSR_JETO INT64_C(0x0200000000000000) /* JBus Timeout */
#define C_AFSR_SCE INT64_C(0x0100000000000000) /* Snoop parity error */
#define C_AFSR_JEIC INT64_C(0x0080000000000000) /* JBus Illegal Cmd */
#define C_AFSR_JEIT INT64_C(0x0040000000000000) /* Illegal ADTYPE */
#define C_AFSR_JEIS INT64_C(0x0008000000000000) /* Illegal Install State */
#define C_AFSR_ETU INT64_C(0x0001000000000000) /* L2$ tag CE error */
#define C_AFSR_ETP INT64_C(0x0001000000000000) /* L2$ tag parity error */
#define C_AFSR_OM INT64_C(0x0000800000000000) /* out of range mem error */
#define C_AFSR_UMS INT64_C(0x0000400000000000) /* Unsupported store */
#define C_AFSR_IVPE INT64_C(0x0000200000000000) /* intr vector parity err */
#define C_AFSR_RUE INT64_C(0x0000000100000000) /* remote mem UE error */
#define C_AFSR_RCE INT64_C(0x0000000080000000) /* remote mem CE error */
#define C_AFSR_BP INT64_C(0x0000000040000000) /* read data parity err */
#define C_AFSR_WBP INT64_C(0x0000000020000000) /* wb/bs data parity err */
#define C_AFSR_FRC INT64_C(0x0000000010000000) /* foregin mem CE error */
#define C_AFSR_FRU INT64_C(0x0000000008000000) /* foregin mem UE error */
#define C_AFSR_JREQ INT64_C(0x0000000007000000) /* Active JBus req at err */
#define C_AFSR_ETW INT64_C(0x0000000000c00000) /* AID causing UE/CE */
#define C_AFSR_EFES INT64_C(0x0000000000200000) /* E-fuse error summary */
#define C_AFSR_ETS INT64_C(0x0000000000100000) /* L2$ tag SRAM stuck-at */
#define C_AFSR_B_SYND INT64_C(0x00000000000f0000) /* jbus parity syndrome */
#define C_AFSR_ETI INT64_C(0x0000000000008000) /* L2$ tag intermittent */
#define C_AFSR_ETC INT64_C(0x0000000000004000) /* L2$ tag CE */
#define C_AFSR_AID INT64_C(0x0000000000003e00) /* AID causing UE/CE */
#define EN_REG_UCEEN INT64_C(0x0000000000000008) /* enable UCC,UCU */
#define EN_REG_ISAPEN INT64_C(0x0000000000000004) /* enable ISAP */
#define EN_REG_NCEEN INT64_C(0x0000000000000002) /* UE,EDU,WDU,BERR,IVU,EMU */
#define EN_REG_CEEN INT64_C(0x0000000000000001) /* enable CE,EDC,WDC,IVC,EMC */
#define EN_REG_DISABLE INT64_C(0x0000000000000000) /* no errors enabled */
#define ECCR_ASSOC INT64_C(0x0000000001000000) /* Ecache Assoc. */
#define EN_REG_FMT INT64_C(0x0000000000040000) /* force system mtag ECC */
#define EN_REG_FMECC INT64_C(0x000000000003C000) /* forced mtag ECC vector */
#define EN_REG_FMD INT64_C(0x0000000000002000) /* force system data ECC */
#define EN_REG_FDECC INT64_C(0x0000000000001ff0) /* forced data ECC vector */
#define EN_REG_UCEEN INT64_C(0x0000000000000008) /* enable UCC,UCU */
#define EN_REG_ISAPEN INT64_C(0x0000000000000004) /* enable ISAP */
#define EN_REG_NCEEN INT64_C(0x0000000000000002) /* UE,EDU,WDU,BERR,IVU,EMU */
#define EN_REG_CEEN INT64_C(0x0000000000000001) /* enable CE,EDC,WDC,IVC,EMC */
#define EN_REG_DISABLE INT64_C(0x0000000000000000) /* no errors enabled */
#define PN_L2_WAY_LIM INT64_C(0x200000)
#define PN_L3_WAY_LIM INT64_C(0x2000000)
#define DCU_IC INT64_C(0x0000000000000001) /* icache enable */
#define DCU_DC INT64_C(0x0000000000000002) /* dcache enable */
#define DCU_IM INT64_C(0x0000000000000004) /* immu enable */
#define DCU_DM INT64_C(0x0000000000000008) /* dmmu enable */
#define DCU_WIH INT64_C(0x0000000000000010) /* Jaguar only - W$ hash index */
#define DCU_VW INT64_C(0x0000000000200000) /* virt watchpoint write enable */
#define DCU_VR INT64_C(0x0000000000400000) /* virt watchpoint read enable */
#define DCU_PW INT64_C(0x0000000000800000) /* phys watchpoint write enable */
#define DCU_PR INT64_C(0x0000000001000000) /* phys watchpoint read enable */
#define JP_ECACHE_IDX_DISP_FLUSH INT64_C(0x0000000080000000)
#define DCU_VM INT64_C(0x00000001FE000000) /* virtual watchpoint write mask */
#define DCU_PM INT64_C(0x000001FE00000000) /* phys watchpoint write mask */
#define DCU_WE INT64_C(0x0000020000000000) /* write cache enable */
#define DCU_SL INT64_C(0x0000040000000000) /* second load control */
#define DCU_SPE INT64_C(0x0000080000000000) /* software prefetch enable */
#define DCU_HPE INT64_C(0x0000100000000000) /* hardware prefetch enable */
#define CHP_ECACHE_IDX_TAG_ECC INT64_C(0x0000000000800000)
#define CHP_ECACHE_IDX_DISP_FLUSH INT64_C(0x0000000001000000)
#define PN_L2_IDX_DISP_FLUSH INT64_C(0x0000000000800000)
#define PN_L3_IDX_DISP_FLUSH INT64_C(0x0000000004000000)
#define DCU_PE INT64_C(0x0000200000000000) /* prefetch enable */
#define DCU_RE INT64_C(0x0000400000000000) /* RAW bypass enable */
#define CH_DCTAG_PA_MASK INT64_C(0x000007ffffffe000)
#define CH_DCTAG_VALID_BIT INT64_C(0x0000000000000001)
#define DCU_ME INT64_C(0x0000800000000000) /* noncache store merging enable */
#define CH_DCSNTAG_MASK INT64_C(0x000007ffffffe000)
#define DCU_CV INT64_C(0x0001000000000000) /* virt cacheability when DM=0 */
#define CHP_DCTAG_PARMASK INT64_C(0x000000007ffffffe)
#define CHP_DCSNTAG_PARMASK INT64_C(0x000000007ffffffe)
#define CHP_DCTAG_MASK INT64_C(0x000003ffffffe000)
#define CHP_DCSNTAG_MASK INT64_C(0x000003ffffffe000)
#define CHP_DCWAY_MASK INT64_C(0x0000000000003fe0)
#define DCU_CP INT64_C(0x0002000000000000) /* phys cacheable when DM,IM=0 */
#define PN_L2_IDX_HW_ECC_EN INT64_C(0x0000000000400000)
#define PN_L3_IDX_HW_ECC_EN INT64_C(0x0000000002000000)
#define UGESR_IUG_DTLB INT64_C(0x0000000000000400)
#define UGESR_IUG_ITLB INT64_C(0x0000000000000200)
#define UGESR_IUG_COREERR INT64_C(0x0000000000000100)
#define UGESR_PRIV INT64_C(0x0000000000000008)
#define UGESR_MULTI_DAE INT64_C(0x0000000000000004)
#define UGESR_MULTI_IAE INT64_C(0x0000000000000002)
#define UGESR_MULTI_UGE INT64_C(0x0000000000000001)
#define ASI_ECR_RTE_UE INT64_C(0x0000000000000200)
#define ASI_ECR_RTE_CEDG INT64_C(0x0000000000000100)
#define ASI_ECR_WEAK_ED INT64_C(0x0000000000000002)
#define ASI_ECR_UGE_HANDLER INT64_C(0x0000000000000001)
#define ASI_L2_CTRL_UGE_TRAP INT64_C(0x0000000001000000)
#define ASI_L2_CTRL_NUMINSWAY_MASK INT64_C(0x0000000000070000)
#define ASI_L2_CTRL_U2_FLUSH INT64_C(0x0000000000000001)
#define SFSR_MK_UE INT64_C(0x0000400000000000)
#define SFSR_EID_MOD INT64_C(0x0000300000000000)
#define SFSR_EID_SID INT64_C(0x00000FFF00000000)
#define SFSR_UE INT64_C(0x0000000080000000)
#define SFSR_BERR INT64_C(0x0000000040000000)
#define SFSR_TO INT64_C(0x0000000020000000)
#define SFSR_TLB_MUL INT64_C(0x0000000008000000)
#define SFSR_TLB_PRT INT64_C(0x0000000004000000)
#define ERRLOG_REG_LOGPA_MASK INT64_C(0x0003ffffffffffc0) /* PA to log */
#define ERRLOG_REG_NUMERR_MASK INT64_C(0x000000000000003f) /* Counter */
#define ERRLOG_REG_EIDR_MASK INT64_C(0x0000000000003fff) /* EIDR */
#define MCNTL_FW_FDTLB INT64_C(0x0000000000004000)
#define MCNTL_FW_FITLB INT64_C(0x0000000000008000)
#define MCNTL_JPS1_TSBP INT64_C(0x0000000000000100)
#define MCNTL_MPG_SITLB INT64_C(0x0000000000000080)
#define MCNTL_MPG_SDTLB INT64_C(0x0000000000000040)
#define UGESR_IAUG_CRE INT64_C(0x0000000000400000)
#define UGESR_IAUG_TSBCTXT INT64_C(0x0000000000200000)
#define UGESR_IUG_TSBP INT64_C(0x0000000000100000)
#define UGESR_IUG_PSTATE INT64_C(0x0000000000080000)
#define UGESR_IUG_TSTATE INT64_C(0x0000000000040000)
#define UGESR_IUG_F INT64_C(0x0000000000020000)
#define UGESR_IUG_R INT64_C(0x0000000000010000)
#define UGESR_AUG_SDC INT64_C(0x0000000000008000)
#define UGESR_IUG_WDT INT64_C(0x0000000000004000)
#define HB_ESTAR_MODE INT64_C(0x1FE0000F080) /* estar mode reg */
#define HB_MEM_CNTRL0 INT64_C(0x1FE0000F010) /* mem control0 reg */
#define HB_REFRESH_INTERVAL INT64_C(7800) /* 7800 nsecs memory */
#define HB_REFRESH_CLOCKS_PER_COUNT INT64_C(64) /* cpu clks per count */
#define HB_ECLK_1 INT64_C(0x0000000000000000) /* 1/1 clock */
#define HB_ECLK_2 INT64_C(0x0000000000000001) /* 1/2 clock */
#define HB_ECLK_4 INT64_C(0x0000000000000003) /* 1/4 clock */
#define HB_ECLK_6 INT64_C(0x0000000000000002) /* 1/6 clock */
#define HB_ECLK_8 INT64_C(0x0000000000000004) /* 1/8 clock */
#define C_AFAR_PA INT64_C(0x000007fffffffff0) /* PA<42:4> physical address */