usr/src/common/mc/imc/imc_decode.c

324

case IMC_GEN_IVY:

usr/src/common/mc/imc/imc_decode.c

532

case IMC_GEN_IVY:

usr/src/test/os-tests/tests/imc/imc_test_sad.c

450

.imc_gen = IMC_GEN_IVY,

usr/src/test/os-tests/tests/imc/imc_test_sad.c

587

.imc_gen = IMC_GEN_IVY,

usr/src/test/os-tests/tests/imc/imc_test_tad.c

135

.imc_gen = IMC_GEN_IVY,

usr/src/test/os-tests/tests/imc/imc_test_tad.c

473

.imc_gen = IMC_GEN_IVY,

usr/src/uts/intel/io/imc/imc.c

1037

case IMC_GEN_IVY:

usr/src/uts/intel/io/imc/imc.c

1230

case IMC_GEN_IVY:

usr/src/uts/intel/io/imc/imc.c

1505

case IMC_GEN_IVY:

usr/src/uts/intel/io/imc/imc.c

1609

if (imc->imc_gen >= IMC_GEN_IVY && imc->imc_gen < IMC_GEN_SKYLAKE) {

usr/src/uts/intel/io/imc/imc.c

1921

case IMC_GEN_IVY:

usr/src/uts/intel/io/imc/imc.c

1955

case IMC_GEN_IVY:

usr/src/uts/intel/io/imc/imc.c

448

{ IMC_GEN_IVY, IMC_TYPE_MC0_MAIN0, 0x0ea8, 15, 0, "IMC 0 Main 0" },

usr/src/uts/intel/io/imc/imc.c

449

{ IMC_GEN_IVY, IMC_TYPE_MC0_MAIN1, 0x0e71, 15, 1, "IMC 0 Main 1" },

usr/src/uts/intel/io/imc/imc.c

450

{ IMC_GEN_IVY, IMC_TYPE_MC0_CHANNEL0, 0x0eaa, 15, 2, "IMC 0 Channel 0 Info" },

usr/src/uts/intel/io/imc/imc.c

451

{ IMC_GEN_IVY, IMC_TYPE_MC0_CHANNEL1, 0x0eab, 15, 3, "IMC 0 Channel 1 Info" },

usr/src/uts/intel/io/imc/imc.c

452

{ IMC_GEN_IVY, IMC_TYPE_MC0_CHANNEL2, 0x0eac, 15, 4, "IMC 0 Channel 2 Info" },

usr/src/uts/intel/io/imc/imc.c

453

{ IMC_GEN_IVY, IMC_TYPE_MC0_CHANNEL3, 0x0ead, 15, 5, "IMC 0 Channel 3 Info" },

usr/src/uts/intel/io/imc/imc.c

454

{ IMC_GEN_IVY, IMC_TYPE_MC1_MAIN0, 0x0e68, 29, 0, "IMC 1 Main 0" },

usr/src/uts/intel/io/imc/imc.c

455

{ IMC_GEN_IVY, IMC_TYPE_MC1_MAIN1, 0x0e79, 29, 1, "IMC 1 Main 1" },

usr/src/uts/intel/io/imc/imc.c

456

{ IMC_GEN_IVY, IMC_TYPE_MC1_CHANNEL0, 0x0e6a, 15, 2, "IMC 1 Channel 0 Info" },

usr/src/uts/intel/io/imc/imc.c

457

{ IMC_GEN_IVY, IMC_TYPE_MC1_CHANNEL1, 0x0e6b, 15, 3, "IMC 1 Channel 1 Info" },

usr/src/uts/intel/io/imc/imc.c

458

{ IMC_GEN_IVY, IMC_TYPE_MC1_CHANNEL2, 0x0e6c, 15, 4, "IMC 1 Channel 2 Info" },

usr/src/uts/intel/io/imc/imc.c

459

{ IMC_GEN_IVY, IMC_TYPE_MC1_CHANNEL3, 0x0e6d, 15, 5, "IMC 1 Channel 3 Info" },

usr/src/uts/intel/io/imc/imc.c

460

{ IMC_GEN_IVY, IMC_TYPE_SAD_DRAM, 0x0ec8, 22, 0, "SAD DRAM Rules" },

usr/src/uts/intel/io/imc/imc.c

461

{ IMC_GEN_IVY, IMC_TYPE_SAD_MMIO, 0x0ec9, 22, 1, "SAD MMIO Rules" },

usr/src/uts/intel/io/imc/imc.c

462

{ IMC_GEN_IVY, IMC_TYPE_SAD_MISC, 0x0eca, 22, 2, "SAD Memory Map" },

usr/src/uts/intel/io/imc/imc.c

463

{ IMC_GEN_IVY, IMC_TYPE_UBOX, 0x0e1e, 11, 0, "UBox" },

usr/src/uts/intel/io/imc/imc.c

464

{ IMC_GEN_IVY, IMC_TYPE_UBOX_CPUBUSNO, 0x0e1f, 11, 3, "UBox Scratch" },

usr/src/uts/intel/io/imc/imc.c

465

{ IMC_GEN_IVY, IMC_TYPE_HA0, 0x0ea0, 14, 0, "Home Agent 0" },

usr/src/uts/intel/io/imc/imc.c

466

{ IMC_GEN_IVY, IMC_TYPE_HA1, 0x0e60, 28, 0, "Home Agent 1" },

usr/src/uts/intel/io/imc/imc.c

588

case IMC_GEN_IVY: