usr/src/common/mc/imc/imc_decode.c

325

case IMC_GEN_HASWELL:

usr/src/common/mc/imc/imc_decode.c

533

case IMC_GEN_HASWELL:

usr/src/test/os-tests/tests/imc/imc_test_rir.c

277

.imc_gen = IMC_GEN_HASWELL,

usr/src/test/os-tests/tests/imc/imc_test_sad.c

730

.imc_gen = IMC_GEN_HASWELL,

usr/src/test/os-tests/tests/imc/imc_test_tad.c

236

.imc_gen = IMC_GEN_HASWELL,

usr/src/uts/intel/io/imc/imc.c

1040

case IMC_GEN_HASWELL:

usr/src/uts/intel/io/imc/imc.c

1122

case IMC_GEN_HASWELL:

usr/src/uts/intel/io/imc/imc.c

1146

if (imc->imc_gen >= IMC_GEN_HASWELL) {

usr/src/uts/intel/io/imc/imc.c

1233

case IMC_GEN_HASWELL:

usr/src/uts/intel/io/imc/imc.c

1314

if (imc->imc_gen >= IMC_GEN_HASWELL) {

usr/src/uts/intel/io/imc/imc.c

1511

case IMC_GEN_HASWELL:

usr/src/uts/intel/io/imc/imc.c

1922

case IMC_GEN_HASWELL:

usr/src/uts/intel/io/imc/imc.c

1956

case IMC_GEN_HASWELL:

usr/src/uts/intel/io/imc/imc.c

2085

if (imc->imc_gen >= IMC_GEN_HASWELL) {

usr/src/uts/intel/io/imc/imc.c

2117

if (imc->imc_gen >= IMC_GEN_HASWELL) {

usr/src/uts/intel/io/imc/imc.c

468

{ IMC_GEN_HASWELL, IMC_TYPE_MC0_MAIN0, 0x2fa8, 19, 0, "IMC 0 Main 0" },

usr/src/uts/intel/io/imc/imc.c

469

{ IMC_GEN_HASWELL, IMC_TYPE_MC0_MAIN1, 0x2f71, 19, 1, "IMC 0 Main 1" },

usr/src/uts/intel/io/imc/imc.c

470

{ IMC_GEN_HASWELL, IMC_TYPE_MC0_CHANNEL0, 0x2faa, 19, 2, "IMC 0 Channel 0 Info" },

usr/src/uts/intel/io/imc/imc.c

471

{ IMC_GEN_HASWELL, IMC_TYPE_MC0_CHANNEL1, 0x2fab, 19, 3, "IMC 0 Channel 1 Info" },

usr/src/uts/intel/io/imc/imc.c

472

{ IMC_GEN_HASWELL, IMC_TYPE_MC0_CHANNEL2, 0x2fac, 19, 4, "IMC 0 Channel 2 Info" },

usr/src/uts/intel/io/imc/imc.c

473

{ IMC_GEN_HASWELL, IMC_TYPE_MC0_CHANNEL3, 0x2fad, 19, 5, "IMC 0 Channel 3 Info" },

usr/src/uts/intel/io/imc/imc.c

474

{ IMC_GEN_HASWELL, IMC_TYPE_MC1_MAIN0, 0x2f68, 22, 0, "IMC 1 Main 0" },

usr/src/uts/intel/io/imc/imc.c

475

{ IMC_GEN_HASWELL, IMC_TYPE_MC1_MAIN1, 0x2f79, 22, 1, "IMC 1 Main 1" },

usr/src/uts/intel/io/imc/imc.c

476

{ IMC_GEN_HASWELL, IMC_TYPE_MC1_CHANNEL0, 0x2f6a, 22, 2, "IMC 1 Channel 0 Info" },

usr/src/uts/intel/io/imc/imc.c

477

{ IMC_GEN_HASWELL, IMC_TYPE_MC1_CHANNEL1, 0x2f6b, 22, 3, "IMC 1 Channel 1 Info" },

usr/src/uts/intel/io/imc/imc.c

478

{ IMC_GEN_HASWELL, IMC_TYPE_MC1_CHANNEL2, 0x2f6c, 22, 4, "IMC 1 Channel 2 Info" },

usr/src/uts/intel/io/imc/imc.c

479

{ IMC_GEN_HASWELL, IMC_TYPE_MC1_CHANNEL3, 0x2f6d, 22, 5, "IMC 1 Channel 3 Info" },

usr/src/uts/intel/io/imc/imc.c

480

{ IMC_GEN_HASWELL, IMC_TYPE_SAD_DRAM, 0x2ffc, 15, 4, "SAD DRAM Rules" },

usr/src/uts/intel/io/imc/imc.c

481

{ IMC_GEN_HASWELL, IMC_TYPE_SAD_MMIO, 0x2ffd, 15, 5, "SAD MMIO Rules" },

usr/src/uts/intel/io/imc/imc.c

482

{ IMC_GEN_HASWELL, IMC_TYPE_VTD_MISC, 0x2f28, 5, 0, "Misc. Vritualization" },

usr/src/uts/intel/io/imc/imc.c

483

{ IMC_GEN_HASWELL, IMC_TYPE_UBOX, 0x2f1e, 16, 5, "UBox" },

usr/src/uts/intel/io/imc/imc.c

484

{ IMC_GEN_HASWELL, IMC_TYPE_UBOX_CPUBUSNO, 0x2f1f, 16, 7, "UBox Scratch" },

usr/src/uts/intel/io/imc/imc.c

485

{ IMC_GEN_HASWELL, IMC_TYPE_HA0, 0x2fa0, 18, 0, "Home Agent 0" },

usr/src/uts/intel/io/imc/imc.c

486

{ IMC_GEN_HASWELL, IMC_TYPE_HA1, 0x2f60, 18, 4, "Home Agent 1" },

usr/src/uts/intel/io/imc/imc.c

591

case IMC_GEN_HASWELL:

usr/src/uts/intel/io/imc/imc.c

923

if (imc->imc_gen >= IMC_GEN_HASWELL) {