Symbol: IEEE1394_CSR_OFFSET_MASK
usr/src/uts/common/io/1394/s1394_csr.c
1170
offset = (req->cmd_addr & IEEE1394_CSR_OFFSET_MASK);
usr/src/uts/common/io/1394/s1394_csr.c
455
offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK;
usr/src/uts/common/io/1394/s1394_csr.c
561
offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK;
usr/src/uts/common/io/1394/s1394_csr.c
663
offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK;
usr/src/uts/common/io/1394/s1394_csr.c
738
offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK;
usr/src/uts/common/io/1394/s1394_csr.c
741
if ((offset == (IEEE1394_CSR_TEST_STATUS & IEEE1394_CSR_OFFSET_MASK)) &&
usr/src/uts/common/io/1394/s1394_csr.c
810
offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK;
usr/src/uts/common/io/1394/s1394_csr.c
887
offset = req->cmd_addr & IEEE1394_CSR_OFFSET_MASK;
usr/src/uts/common/io/1394/s1394_csr.c
996
offset = (req->cmd_addr & IEEE1394_CSR_OFFSET_MASK);
usr/src/uts/common/io/1394/s1394_dev_disc.c
1852
IEEE1394_CSR_OFFSET_MASK), S1394_INVALID_NODE_NUM,
usr/src/uts/common/io/1394/s1394_isoch.c
323
(IEEE1394_SCSR_CHANS_AVAIL_HI & IEEE1394_CSR_OFFSET_MASK);
usr/src/uts/common/io/1394/s1394_isoch.c
326
(IEEE1394_SCSR_CHANS_AVAIL_LO & IEEE1394_CSR_OFFSET_MASK);
usr/src/uts/common/io/1394/s1394_isoch.c
478
(IEEE1394_SCSR_CHANS_AVAIL_HI & IEEE1394_CSR_OFFSET_MASK);
usr/src/uts/common/io/1394/s1394_isoch.c
481
(IEEE1394_SCSR_CHANS_AVAIL_LO & IEEE1394_CSR_OFFSET_MASK);
usr/src/uts/common/io/1394/s1394_isoch.c
629
IEEE1394_CSR_OFFSET_MASK), &old_value);
usr/src/uts/common/io/1394/s1394_isoch.c
652
IEEE1394_CSR_OFFSET_MASK), compare, swap,
usr/src/uts/common/io/1394/s1394_isoch.c
806
IEEE1394_CSR_OFFSET_MASK), &old_value);
usr/src/uts/common/io/1394/s1394_isoch.c
827
IEEE1394_CSR_OFFSET_MASK), compare, swap,
usr/src/uts/common/io/1394/s1394_misc.c
867
offset = (IEEE1394_CSR_STATE_SET & IEEE1394_CSR_OFFSET_MASK);