IDLE_CHK_ERROR_NO_TRAFFIC
IDLE_CHK_2(0x2, QM_REG_QTASKCTR_EXT_A_0, 64, 4, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Q_EXT_A (upper 64 queues), Queue is not empty");
IDLE_CHK_1(0x1E, QM_REG_PAUSESTATE2, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: PAUSESTATE2 is not 0");
IDLE_CHK_1(0x1E, QM_REG_PAUSESTATE3, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: PAUSESTATE3 is not 0");
IDLE_CHK_6(0x2, QM_REG_PTRTBL_EXT_A, 64, 8, IDLE_CHK_ERROR_NO_TRAFFIC);
IDLE_CHK_3(0xC, QM_REG_BYTECRD0, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 0 is not equal to initial credit");
IDLE_CHK_3(0xC, QM_REG_BYTECRD1, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 1 is not equal to initial credit");
IDLE_CHK_3(0xC, QM_REG_BYTECRD2, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 2 is not equal to initial credit");
IDLE_CHK_3(0x10, QM_REG_VOQCREDIT_0, QM_REG_VOQINITCREDIT_0, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_0, VOQ credit is not equal to initial credit");
IDLE_CHK_3(0x10, QM_REG_VOQCREDIT_1, QM_REG_VOQINITCREDIT_1, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_1, VOQ credit is not equal to initial credit");
IDLE_CHK_3(0x10, QM_REG_VOQCREDIT_2, QM_REG_VOQINITCREDIT_2, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_2, VOQ credit is not equal to initial credit");
IDLE_CHK_3(0x10, QM_REG_VOQCREDIT_3, QM_REG_VOQINITCREDIT_3, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_3, VOQ credit is not equal to initial credit");
IDLE_CHK_3(0x10, QM_REG_VOQCREDIT_4, QM_REG_VOQINITCREDIT_4, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_4, VOQ credit is not equal to initial credit");
IDLE_CHK_3(0x10, QM_REG_VOQCREDIT_5, QM_REG_VOQINITCREDIT_5, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_5, VOQ credit is not equal to initial credit");
IDLE_CHK_3(0x10, QM_REG_VOQCREDIT_6, QM_REG_VOQINITCREDIT_6, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_6 (LB VOQ), VOQ credit is not equal to initial credit");
IDLE_CHK_3(0x10, QM_REG_BYTECRD0, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 0 is not equal to initial credit");
IDLE_CHK_3(0x10, QM_REG_BYTECRD1, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 1 is not equal to initial credit");
IDLE_CHK_3(0x10, QM_REG_BYTECRD2, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 2 is not equal to initial credit");
IDLE_CHK_3(0x10, QM_REG_BYTECRD3, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 3 is not equal to initial credit");
IDLE_CHK_3(0x10, QM_REG_BYTECRD4, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 4 is not equal to initial credit");
IDLE_CHK_3(0x10, QM_REG_BYTECRD5, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 5 is not equal to initial credit");
IDLE_CHK_3(0x10, QM_REG_BYTECRD6, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Byte credit 6 is not equal to initial credit");
IDLE_CHK_1(0x1F, NIG_REG_INGRESS_EOP_PORT0_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 0 EOP FIFO is not empty.");
IDLE_CHK_1(0x1F, NIG_REG_INGRESS_EOP_PORT1_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 1 EOP FIFO is not empty.");
IDLE_CHK_1(0x1F, NIG_REG_INGRESS_EOP_LB_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: LB EOP FIFO is not empty.");
IDLE_CHK_1(0x1F, NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: PBF LB FIFO is not empty.");
IDLE_CHK_1(0x1F, NIG_REG_EGRESS_DEBUG_FIFO_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Debug FIFO is not empty.");
IDLE_CHK_1(0x1F, NIG_REG_EGRESS_DELAY0_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: PBF IF0 FIFO is not empty.");
IDLE_CHK_1(0x1F, NIG_REG_EGRESS_DELAY1_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: PBF IF1 FIFO is not empty.");
IDLE_CHK_1(0x1F, NIG_REG_LLH0_FIFO_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 0 RX LLH FIFO is not empty.");
IDLE_CHK_1(0x1F, NIG_REG_LLH1_FIFO_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 1 RX LLH FIFO is not empty.");
IDLE_CHK_1(0x1C, NIG_REG_P0_TLLH_FIFO_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 0 TX LLH FIFO is not empty.");
IDLE_CHK_1(0x1C, NIG_REG_P1_TLLH_FIFO_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 1 TX LLH FIFO is not empty.");
IDLE_CHK_1(0x18, NIG_REG_P0_RX_MACFIFO_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 0 RX MAC interface FIFO is not empty.");
IDLE_CHK_1(0x18, NIG_REG_P1_RX_MACFIFO_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 1 RX MAC interface FIFO is not empty.");
IDLE_CHK_1(0x18, NIG_REG_P0_TX_MACFIFO_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 0 TX MAC interface FIFO is not empty.");
IDLE_CHK_1(0x18, NIG_REG_P1_TX_MACFIFO_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: Port 1 TX MAC interface FIFO is not empty.");
IDLE_CHK_1(0x10, NIG_REG_EGRESS_DELAY2_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: PBF IF2 FIFO is not empty.");
IDLE_CHK_1(0x10, NIG_REG_EGRESS_DELAY3_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: PBF IF3 FIFO is not empty.");
IDLE_CHK_1(0x10, NIG_REG_EGRESS_DELAY4_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: PBF IF4 FIFO is not empty.");
IDLE_CHK_1(0x10, NIG_REG_EGRESS_DELAY5_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "NIG: PBF IF5 FIFO is not empty.");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ0_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ0 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ1_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ1 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ2_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ2 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ3_ENTRY_CNT, (val > 2), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ3 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ4_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ4 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ5_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ5 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ6_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ6 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ7_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ7 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ8_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ8 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ9_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ9 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ10_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ10 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ11_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ11 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ12_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ12 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ13_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ13 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ14_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ14 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ15_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ15 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ16_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ16 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ17_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ17 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ18_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ18 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ19_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ19 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ20_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ20 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ21_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ21 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ22_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ22 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ23_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ23 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ24_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ24 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ25_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ25 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ26_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ26 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ27_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ27 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ28_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ28 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ29_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ29 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ30_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ30 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_VQ31_ENTRY_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: VQ31 is not empty");
IDLE_CHK_1(0x1F, PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: rq_ufifo_num_of_entry is not 0");
IDLE_CHK_1(0x3, PXP2_REG_PSWRQ_BW_CREDIT, (val != 0x1B), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: rq_read_credit and rq_write_credit are not 3");
IDLE_CHK_3(0x1F, PXP2_REG_RD_SR_CNT, PXP2_REG_RD_SR_NUM_CFG, (val1 < (val2-3)), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: There are more than two unused SRs");
IDLE_CHK_3(0x1F, PXP2_REG_RD_BLK_CNT, PXP2_REG_RD_BLK_NUM_CFG, (val1 < (val2-2)), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: There are more than two unused blocks");
IDLE_CHK_1(0x1F, PXP2_REG_RD_PORT_IS_IDLE_0, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: P0 All delivery ports are not idle");
IDLE_CHK_1(0x1F, PXP2_REG_RD_PORT_IS_IDLE_1, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: P1 All delivery ports are not idle");
IDLE_CHK_2(0x1F, PXP2_REG_RD_ALMOST_FULL_0, 11, 4, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: rd_almost_full is not 0");
IDLE_CHK_1(0x1F, PXP2_REG_HST_HEADER_FIFO_STATUS, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: HST header FIFO status is not 0");
IDLE_CHK_1(0x1F, PXP2_REG_HST_DATA_FIFO_STATUS, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: HST data FIFO status is not 0");
IDLE_CHK_1(0x1F, PXP2_REG_PGL_TXW_CDTS, (((val >> 17) & 1) != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PXP2: There is data which is ready");
IDLE_CHK_1(0x1F, DMAE_REG_GO_C0, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 0 go is not 0");
IDLE_CHK_1(0x1F, DMAE_REG_GO_C1, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 1 go is not 0");
IDLE_CHK_1(0x1F, DMAE_REG_GO_C2, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 2 go is not 0");
IDLE_CHK_1(0x1F, DMAE_REG_GO_C3, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 3 go is not 0");
IDLE_CHK_1(0x1F, DMAE_REG_GO_C4, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 4 go is not 0");
IDLE_CHK_1(0x1F, DMAE_REG_GO_C5, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 5 go is not 0");
IDLE_CHK_1(0x1F, DMAE_REG_GO_C6, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 6 go is not 0");
IDLE_CHK_1(0x1F, DMAE_REG_GO_C7, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 7 go is not 0");
IDLE_CHK_1(0x1F, DMAE_REG_GO_C8, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 8 go is not 0");
IDLE_CHK_1(0x1F, DMAE_REG_GO_C9, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 9 go is not 0");
IDLE_CHK_1(0x1F, DMAE_REG_GO_C10, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 10 go is not 0");
IDLE_CHK_1(0x1F, DMAE_REG_GO_C11, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 11 go is not 0");
IDLE_CHK_1(0x1F, DMAE_REG_GO_C12, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 12 go is not 0");
IDLE_CHK_1(0x1F, DMAE_REG_GO_C13, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 13 go is not 0");
IDLE_CHK_1(0x1F, DMAE_REG_GO_C14, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 14 go is not 0");
IDLE_CHK_1(0x1F, DMAE_REG_GO_C15, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DMAE: command 15 go is not 0");
IDLE_CHK_7(0x1F, CFC_REG_ACTIVITY_COUNTER, CFC_REG_INFO_RAM, CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, ((val1 == 0) && (val2 != 0) && (val2 != 2)), IDLE_CHK_ERROR_NO_TRAFFIC, "CFC: AC is neither 0 nor 2 on connType 0 (ETH)");
IDLE_CHK_7(0x1F, CFC_REG_ACTIVITY_COUNTER, CFC_REG_INFO_RAM, CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, ((val1 == 1) && (val2 != 0)), IDLE_CHK_ERROR_NO_TRAFFIC, "CFC: AC is not 0 on connType 1 (TOE)");
IDLE_CHK_7(0x1F, CFC_REG_ACTIVITY_COUNTER, CFC_REG_INFO_RAM, CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, ((val1 == 3) && (val2 != 0)), IDLE_CHK_ERROR_NO_TRAFFIC, "CFC: AC is not 0 on connType 3 (iSCSI)");
IDLE_CHK_7(0x1F, CFC_REG_ACTIVITY_COUNTER, CFC_REG_INFO_RAM, CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, ((val1 == 4) && (val2 != 0)), IDLE_CHK_ERROR_NO_TRAFFIC, "CFC: AC is not 0 on connType 4 (FCoE)");
IDLE_CHK_2(0x1F, QM_REG_QTASKCTR_0, 64, 4, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: Queue is not empty");
IDLE_CHK_3(0xF, QM_REG_VOQCREDIT_0, QM_REG_VOQINITCREDIT_0, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_0, VOQ credit is not equal to initial credit");
IDLE_CHK_3(0xF, QM_REG_VOQCREDIT_1, QM_REG_VOQINITCREDIT_1, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_1, VOQ credit is not equal to initial credit");
IDLE_CHK_3(0xF, QM_REG_VOQCREDIT_4, QM_REG_VOQINITCREDIT_4, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: VOQ_4, VOQ credit is not equal to initial credit");
IDLE_CHK_3(0x3, QM_REG_PORT0BYTECRD, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: P0 Byte credit is not equal to initial credit");
IDLE_CHK_3(0x3, QM_REG_PORT1BYTECRD, QM_REG_BYTECRDINITVAL, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: P1 Byte credit is not equal to initial credit");
IDLE_CHK_1(0x1F, CCM_REG_CAM_OCCUP, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: XX protection CAM is not empty");
IDLE_CHK_1(0x1F, TCM_REG_CAM_OCCUP, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "TCM: XX protection CAM is not empty");
IDLE_CHK_1(0x1F, UCM_REG_CAM_OCCUP, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: XX protection CAM is not empty");
IDLE_CHK_1(0x1F, XCM_REG_CAM_OCCUP, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "XCM: XX protection CAM is not empty");
IDLE_CHK_1(0x1F, BRB1_REG_NUM_OF_FULL_BLOCKS, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "BRB1: BRB is not empty");
IDLE_CHK_1(0x1F, CSEM_REG_SLEEP_THREADS_VALID, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "CSEM: There are sleeping threads");
IDLE_CHK_1(0x1F, TSEM_REG_SLEEP_THREADS_VALID, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "TSEM: There are sleeping threads");
IDLE_CHK_1(0x1F, USEM_REG_SLEEP_THREADS_VALID, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "USEM: There are sleeping threads");
IDLE_CHK_1(0x1F, XSEM_REG_SLEEP_THREADS_VALID, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "XSEM: There are sleeping threads");
IDLE_CHK_1(0x1F, CSEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "CSEM: External store FIFO is not empty");
IDLE_CHK_1(0x1F, TSEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "TSEM: External store FIFO is not empty");
IDLE_CHK_1(0x1F, USEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "USEM: External store FIFO is not empty");
IDLE_CHK_1(0x1F, XSEM_REG_SLOW_EXT_STORE_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "XSEM: External store FIFO is not empty");
IDLE_CHK_1(0x1F, CSDM_REG_SYNC_PARSER_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "CSDM: Parser serial FIFO is not empty");
IDLE_CHK_1(0x1F, TSDM_REG_SYNC_PARSER_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "TSDM: Parser serial FIFO is not empty");
IDLE_CHK_1(0x1F, USDM_REG_SYNC_PARSER_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "USDM: Parser serial FIFO is not empty");
IDLE_CHK_1(0x1F, XSDM_REG_SYNC_PARSER_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "XSDM: Parser serial FIFO is not empty");
IDLE_CHK_1(0x1F, CSDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "CSDM: Parser SYNC serial FIFO is not empty");
IDLE_CHK_1(0x1F, TSDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "TSDM: Parser SYNC serial FIFO is not empty");
IDLE_CHK_1(0x1F, USDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "USDM: Parser SYNC serial FIFO is not empty");
IDLE_CHK_1(0x1F, XSDM_REG_SYNC_SYNC_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "XSDM: Parser SYNC serial FIFO is not empty");
IDLE_CHK_1(0x1F, CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "CSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block");
IDLE_CHK_1(0x1F, TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "TSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block");
IDLE_CHK_1(0x1F, USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "USDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block");
IDLE_CHK_1(0x1F, XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "XSDM: pxp_ctrl rd_data fifo is not empty in sdm_dma_rsp block");
IDLE_CHK_1(0x1F, DORQ_REG_DQ_FILL_LVLF, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "DORQ: DORQ queue is not empty");
IDLE_CHK_1(0x1F, DORQ_REG_RSPA_CRD_CNT, (val != 2), IDLE_CHK_ERROR_NO_TRAFFIC, "DORQ: Credit to XCM is not full");
IDLE_CHK_1(0x1F, DORQ_REG_RSPB_CRD_CNT, (val != 2), IDLE_CHK_ERROR_NO_TRAFFIC, "DORQ: Credit to UCM is not full");
IDLE_CHK_5(0xF, PBF_REG_DISABLE_NEW_TASK_PROC_P0, PBF_REG_P0_CREDIT, PBF_REG_P0_INIT_CRD, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P0 credit is not equal to init_crd");
IDLE_CHK_5(0xF, PBF_REG_DISABLE_NEW_TASK_PROC_P1, PBF_REG_P1_CREDIT, PBF_REG_P1_INIT_CRD, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P1 credit is not equal to init_crd");
IDLE_CHK_3(0xF, PBF_REG_P4_CREDIT, PBF_REG_P4_INIT_CRD, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P4 credit is not equal to init_crd");
IDLE_CHK_5(0x10, PBF_REG_DISABLE_NEW_TASK_PROC_Q0, PBF_REG_CREDIT_Q0, PBF_REG_INIT_CRD_Q0, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q0 credit is not equal to init_crd");
IDLE_CHK_5(0x10, PBF_REG_DISABLE_NEW_TASK_PROC_Q1, PBF_REG_CREDIT_Q1, PBF_REG_INIT_CRD_Q1, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q1 credit is not equal to init_crd");
IDLE_CHK_5(0x10, PBF_REG_DISABLE_NEW_TASK_PROC_Q2, PBF_REG_CREDIT_Q2, PBF_REG_INIT_CRD_Q2, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q2 credit is not equal to init_crd");
IDLE_CHK_5(0x10, PBF_REG_DISABLE_NEW_TASK_PROC_Q3, PBF_REG_CREDIT_Q3, PBF_REG_INIT_CRD_Q3, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q3 credit is not equal to init_crd");
IDLE_CHK_5(0x10, PBF_REG_DISABLE_NEW_TASK_PROC_Q4, PBF_REG_CREDIT_Q4, PBF_REG_INIT_CRD_Q4, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q4 credit is not equal to init_crd");
IDLE_CHK_5(0x10, PBF_REG_DISABLE_NEW_TASK_PROC_Q5, PBF_REG_CREDIT_Q5, PBF_REG_INIT_CRD_Q5, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q5 credit is not equal to init_crd");
IDLE_CHK_3(0x10, PBF_REG_CREDIT_LB_Q, PBF_REG_INIT_CRD_LB_Q, (val1 != val2), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: LB Q credit is not equal to init_crd");
IDLE_CHK_1(0xF, PBF_REG_P0_TASK_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P0 task_cnt is not 0");
IDLE_CHK_1(0xF, PBF_REG_P1_TASK_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P1 task_cnt is not 0");
IDLE_CHK_1(0xF, PBF_REG_P4_TASK_CNT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: P4 task_cnt is not 0");
IDLE_CHK_1(0x10, PBF_REG_TASK_CNT_Q0, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q0 task_cnt is not 0");
IDLE_CHK_1(0x10, PBF_REG_TASK_CNT_Q1, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q1 task_cnt is not 0");
IDLE_CHK_1(0x10, PBF_REG_TASK_CNT_Q2, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q2 task_cnt is not 0");
IDLE_CHK_1(0x10, PBF_REG_TASK_CNT_Q3, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q3 task_cnt is not 0");
IDLE_CHK_1(0x10, PBF_REG_TASK_CNT_Q4, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q4 task_cnt is not 0");
IDLE_CHK_1(0x10, PBF_REG_TASK_CNT_Q5, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: Q5 task_cnt is not 0");
IDLE_CHK_1(0x10, PBF_REG_TASK_CNT_LB_Q, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PBF: LB Q task_cnt is not 0");
IDLE_CHK_1(0x1F, XCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "XCM: CFC_INIT_CRD is not 1");
IDLE_CHK_1(0x1F, UCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: CFC_INIT_CRD is not 1");
IDLE_CHK_1(0x1F, TCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "TCM: CFC_INIT_CRD is not 1");
IDLE_CHK_1(0x1F, CCM_REG_CFC_INIT_CRD, (val != 1), IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: CFC_INIT_CRD is not 1");
IDLE_CHK_1(0x1F, XCM_REG_XQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR_NO_TRAFFIC, "XCM: XQM_INIT_CRD is not 32");
IDLE_CHK_1(0x1F, UCM_REG_UQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: UQM_INIT_CRD is not 32");
IDLE_CHK_1(0x1F, TCM_REG_TQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR_NO_TRAFFIC, "TCM: TQM_INIT_CRD is not 32");
IDLE_CHK_1(0x1F, CCM_REG_CQM_INIT_CRD, (val != 32), IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: CQM_INIT_CRD is not 32");
IDLE_CHK_1(0x1F, XCM_REG_TM_INIT_CRD, (val != 4), IDLE_CHK_ERROR_NO_TRAFFIC, "XCM: TM_INIT_CRD is not 4");
IDLE_CHK_1(0x1F, UCM_REG_TM_INIT_CRD, (val != 4), IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: TM_INIT_CRD is not 4");
IDLE_CHK_1(0x1F, UCM_REG_FIC0_INIT_CRD, (val != 64), IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: FIC0_INIT_CRD is not 64");
IDLE_CHK_1(0x1F, TCM_REG_FIC0_INIT_CRD, (val != 64), IDLE_CHK_ERROR_NO_TRAFFIC, "TCM: FIC0_INIT_CRD is not 64");
IDLE_CHK_1(0x1F, CCM_REG_FIC0_INIT_CRD, (val != 64), IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: FIC0_INIT_CRD is not 64");
IDLE_CHK_1(0x1F, XCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR_NO_TRAFFIC, "XCM: FIC1_INIT_CRD is not 64");
IDLE_CHK_1(0x1F, UCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: FIC1_INIT_CRD is not 64");
IDLE_CHK_1(0x1F, TCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR_NO_TRAFFIC, "TCM: FIC1_INIT_CRD is not 64");
IDLE_CHK_1(0x1F, CCM_REG_FIC1_INIT_CRD, (val != 64), IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: FIC1_INIT_CRD is not 64");
IDLE_CHK_1(0x1, XCM_REG_XX_FREE, (val != 31), IDLE_CHK_ERROR_NO_TRAFFIC, "XCM: XX_FREE differs from expected 31");
IDLE_CHK_1(0x1E, XCM_REG_XX_FREE, (val != 32), IDLE_CHK_ERROR_NO_TRAFFIC, "XCM: XX_FREE differs from expected 32");
IDLE_CHK_1(0x1F, UCM_REG_XX_FREE, (val != 27), IDLE_CHK_ERROR_NO_TRAFFIC, "UCM: XX_FREE differs from expected 27");
IDLE_CHK_1(0x7, TCM_REG_XX_FREE, (val != 32), IDLE_CHK_ERROR_NO_TRAFFIC, "TCM: XX_FREE differs from expected 32");
IDLE_CHK_1(0x18, TCM_REG_XX_FREE, (val != 29), IDLE_CHK_ERROR_NO_TRAFFIC, "TCM: XX_FREE differs from expected 29");
IDLE_CHK_1(0x1F, CCM_REG_XX_FREE, (val != 24), IDLE_CHK_ERROR_NO_TRAFFIC, "CCM: XX_FREE differs from expected 24");
IDLE_CHK_1(0x1F, XSEM_REG_FAST_MEMORY + 0x18000, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "XSEM: FOC0 credit less than initial credit");
IDLE_CHK_1(0x1F, XSEM_REG_FAST_MEMORY + 0x18040, (val != 24), IDLE_CHK_ERROR_NO_TRAFFIC, "XSEM: FOC1 credit less than initial credit");
IDLE_CHK_1(0x1F, XSEM_REG_FAST_MEMORY + 0x18080, (val != 12), IDLE_CHK_ERROR_NO_TRAFFIC, "XSEM: FOC2 credit less than initial credit");
IDLE_CHK_1(0x1F, USEM_REG_FAST_MEMORY + 0x18000, (val != 26), IDLE_CHK_ERROR_NO_TRAFFIC, "USEM: FOC0 credit less than initial credit");
IDLE_CHK_1(0x1F, USEM_REG_FAST_MEMORY + 0x18040, (val != 78), IDLE_CHK_ERROR_NO_TRAFFIC, "USEM: FOC1 credit less than initial credit");
IDLE_CHK_1(0x1F, USEM_REG_FAST_MEMORY + 0x18080, (val != 16), IDLE_CHK_ERROR_NO_TRAFFIC, "USEM: FOC2 credit less than initial credit");
IDLE_CHK_1(0x1F, USEM_REG_FAST_MEMORY + 0x180C0, (val != 32), IDLE_CHK_ERROR_NO_TRAFFIC, "USEM: FOC3 credit less than initial credit");
IDLE_CHK_1(0x1F, TSEM_REG_FAST_MEMORY + 0x18000, (val != 52), IDLE_CHK_ERROR_NO_TRAFFIC, "TSEM: FOC0 credit less than initial credit");
IDLE_CHK_1(0x1F, TSEM_REG_FAST_MEMORY + 0x18040, (val != 24), IDLE_CHK_ERROR_NO_TRAFFIC, "TSEM: FOC1 credit less than initial credit");
IDLE_CHK_1(0x1F, TSEM_REG_FAST_MEMORY + 0x18080, (val != 12), IDLE_CHK_ERROR_NO_TRAFFIC, "TSEM: FOC2 credit less than initial credit");
IDLE_CHK_1(0x1F, TSEM_REG_FAST_MEMORY + 0x180C0, (val != 32), IDLE_CHK_ERROR_NO_TRAFFIC, "TSEM: FOC3 credit less than initial credit");
IDLE_CHK_1(0x1F, CSEM_REG_FAST_MEMORY + 0x18000, (val != 16), IDLE_CHK_ERROR_NO_TRAFFIC, "CSEM: FOC0 credit less than initial credit");
IDLE_CHK_1(0x1F, CSEM_REG_FAST_MEMORY + 0x18040, (val != 18), IDLE_CHK_ERROR_NO_TRAFFIC, "CSEM: FOC1 credit less than initial credit");
IDLE_CHK_1(0x1F, CSEM_REG_FAST_MEMORY + 0x18080, (val != 48), IDLE_CHK_ERROR_NO_TRAFFIC, "CSEM: FOC2 credit less than initial credit");
IDLE_CHK_1(0x1F, CSEM_REG_FAST_MEMORY + 0x180C0, (val != 14), IDLE_CHK_ERROR_NO_TRAFFIC, "CSEM: FOC3 credit less than initial credit");
IDLE_CHK_1(0x1F, PRS_REG_TSDM_CURRENT_CREDIT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PRS: TSDM current credit is not 0");
IDLE_CHK_1(0x1F, PRS_REG_TCM_CURRENT_CREDIT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PRS: TCM current credit is not 0");
IDLE_CHK_1(0x1F, PRS_REG_CFC_LD_CURRENT_CREDIT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PRS: CFC_LD current credit is not 0");
IDLE_CHK_1(0x1F, PRS_REG_CFC_SEARCH_CURRENT_CREDIT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PRS: CFC_SEARCH current credit is not 0");
IDLE_CHK_1(0x1F, PRS_REG_SRC_CURRENT_CREDIT, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PRS: SRCH current credit is not 0");
IDLE_CHK_1(0x1F, PRS_REG_PENDING_BRB_PRS_RQ, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PRS: PENDING_BRB_PRS_RQ is not 0");
IDLE_CHK_2(0x1F, PRS_REG_PENDING_BRB_CAC0_RQ, 5, 4, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PRS: PENDING_BRB_CAC_RQ is not 0");
IDLE_CHK_1(0x1F, PRS_REG_SERIAL_NUM_STATUS_LSB, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PRS: SERIAL_NUM_STATUS_LSB is not 0");
IDLE_CHK_1(0x1F, PRS_REG_SERIAL_NUM_STATUS_MSB, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "PRS: SERIAL_NUM_STATUS_MSB is not 0");
IDLE_CHK_1(0x1F, QM_REG_XQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: XQM wrc_fifolvl is not 0");
IDLE_CHK_1(0x1F, QM_REG_UQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: UQM wrc_fifolvl is not 0");
IDLE_CHK_1(0x1F, QM_REG_TQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: TQM wrc_fifolvl is not 0");
IDLE_CHK_1(0x1F, QM_REG_CQM_WRC_FIFOLVL, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: CQM wrc_fifolvl is not 0");
IDLE_CHK_1(0x1F, QM_REG_QSTATUS_LOW, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: QSTATUS_LOW is not 0");
IDLE_CHK_1(0x1F, QM_REG_QSTATUS_HIGH, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: QSTATUS_HIGH is not 0");
IDLE_CHK_1(0x1F, QM_REG_PAUSESTATE0, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: PAUSESTATE0 is not 0");
IDLE_CHK_1(0x1F, QM_REG_PAUSESTATE1, (val != 0), IDLE_CHK_ERROR_NO_TRAFFIC, "QM: PAUSESTATE1 is not 0");
IDLE_CHK_6(0x1F, QM_REG_PTRTBL, 64, 8, IDLE_CHK_ERROR_NO_TRAFFIC);
case IDLE_CHK_ERROR_NO_TRAFFIC: \